interface cpu_if # (
    parameter integer C_S00_AXI_DATA_WIDTH   = 32,
    parameter integer C_S00_AXI_ADDR_WIDTH   = 4,
    parameter integer C_M00_AXIS_TDATA_WIDTH = 32,
    parameter integer C_M00_AXIS_START_COUNT = 32,
    parameter integer C_M00_AXI_TARGET_SLAVE_BASE_ADDR = 32'h40000000,
    parameter integer C_M00_AXI_BURST_LEN    = 16,
    parameter integer C_M00_AXI_ID_WIDTH     = 1,
    parameter integer C_M00_AXI_ADDR_WIDTH   = 32,
    parameter integer C_M00_AXI_DATA_WIDTH   = 32,
    parameter integer C_M00_AXI_AWUSER_WIDTH = 0,
    parameter integer C_M00_AXI_ARUSER_WIDTH = 0,
    parameter integer C_M00_AXI_WUSER_WIDTH  = 0,
    parameter integer C_M00_AXI_RUSER_WIDTH  = 0,
    parameter integer C_M00_AXI_BUSER_WIDTH  = 0
) (input bit clk);

    wire [C_S00_AXI_ADDR_WIDTH-1 : 0       ] s00_axi_awaddr;
    wire [2 : 0                            ] s00_axi_awprot;
    wire                                     s00_axi_awvalid;
    wire                                     s00_axi_awready;
    wire [C_S00_AXI_DATA_WIDTH-1 : 0       ] s00_axi_wdata;
    wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0   ] s00_axi_wstrb;
    wire                                     s00_axi_wvalid;
    wire                                     s00_axi_wready;
    wire [1 : 0                            ] s00_axi_bresp;
    wire                                     s00_axi_bvalid;
    wire                                     s00_axi_bready;
    wire [C_S00_AXI_ADDR_WIDTH-1 : 0       ] s00_axi_araddr;
    wire [2 : 0                            ] s00_axi_arprot;
    wire                                     s00_axi_arvalid;
    wire                                     s00_axi_arready;
    wire [C_S00_AXI_DATA_WIDTH-1 : 0       ] s00_axi_rdata;
    wire [1 : 0                            ] s00_axi_rresp;
    wire                                     s00_axi_rvalid;
    wire                                     s00_axi_rready;
 
    clocking axi_lite_cb @(posedge clk);
        output s00_axi_awaddr;
        output s00_axi_awprot;
        output s00_axi_awvalid;
        input  s00_axi_awready;
        output s00_axi_wdata;
        output s00_axi_wstrb;
        output s00_axi_wvalid;
        input  s00_axi_wready;
        input  s00_axi_bresp;
        input  s00_axi_bvalid;
        output s00_axi_bready;
        output s00_axi_araddr;
        output s00_axi_arprot;
        output s00_axi_arvalid;
        input  s00_axi_arready;
        input  s00_axi_rdata;
        input  s00_axi_rresp;
        input  s00_axi_rvalid;
        output s00_axi_rready;
    endclocking

    modport drvprt( clocking axi_lite_cb );

endinterface
